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1 mhz to 10 ghz, 45 db log detector/controller ad8319 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2008 analog devices, inc. all rights reserved. features wide bandwidth: 1 mhz to 10 ghz high accuracy: 1.0 db over temperature 45 db dynamic range up to 8 ghz stability over temperature: 0.5 db low noise measurement/controller output vout pulse response time (fall/rise): 6 ns/10 ns small footprint: 2 mm 3 mm lfcsp supply operation: 3.0 v to 5.5 v @ 22 ma fabricated using high speed sige process applications rf transmitter pa setpoint controls and level monitoring power monitoring in radiolink transmitters rssi measurement in base stations, wlans, wimax, and radars functional block diagram gain bias slope det det det det inhi inlo iv v ou t iv vset clpf tadj v pos comm 05705-001 figure 1. general description the ad8319 is a demodulating logarithmic amplifier, capable of accurately converting an rf input signal to a corresponding decibel-scaled output. it employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. the device can be used in either measurement or controller modes. the ad8319 maintains accurate log conformance for signals of 1 mhz to 8 ghz and provides useful operation to 10 ghz. the input dynamic range is typically 45 db (re: 50 ) with error less than 3 db. the ad8319 has 6 ns/10 ns (fall time/rise time) response time that enables rf burst detection to a pulse rate of beyond 50 mhz. the device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. a supply of 3.0 v to 5.5 v is required to power the device. current consumption is typically 22 ma, and it decreases to 200 a when the device is disabled. the ad8319 can be configured to provide a control voltage to a power amplifier or a measurement output from the vout pin. because the output can be used for controller applications, special attention was paid to minimize wideband noise. in this mode, the setpoint control voltage is applied to the vset pin. the feedback loop through an rf amplifier is closed via vout, the output of which regulates the output of the amplifier to a magnitude corresponding to v set . the ad8319 provides 0 v to (v pos ? 0.1 v) output capability at the vout pin, suitable for controller applications. as a measurement device, vout is externally connected to vset to produce an output voltage, v out , that is a decreasing linear-in-db function of the rf input signal amplitude. the logarithmic slope is ?22 mv/db, determined by the vset interface. the intercept is 15 dbm (re: 50 , cw input) using the inhi input. these parameters are very stable against supply and temperature variations. the ad8319 is fabricated on a sige bipolar ic process and is available in a 2 mm 3 mm, 8-lead lfcsp for an operating temperature range of ?40c to +85c.
ad8319 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 using the ad8319 .......................................................................... 11 basic connections ...................................................................... 11 input signal coupling ................................................................ 11 output interface ......................................................................... 11 setpoint interface ....................................................................... 11 temperature compensation of output voltage ..................... 12 measurement mode ................................................................... 12 setting the output slope in measurement mode .................. 13 controller mode ......................................................................... 13 output filtering .......................................................................... 15 operation beyond 8 ghz ......................................................... 16 evaluation board ............................................................................ 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 4/08rev. a to rev. b changes to features section and general description section . 1 changes to theory of operation section.................................... 10 changes to figure 22 and setpoint interface section................ 11 3/07rev. 0 to rev. a changes to figure 9.......................................................................... 8 changes to figure 22 and setpoint interface section................ 11 changes to measurement mode section..................................... 12 changes to layout .......................................................................... 16 changes to layout .......................................................................... 17 updated outline dimensions ....................................................... 18 10/05revision 0: initial version
ad8319 rev. b | page 3 of 20 specifications v pos = 3 v, c lpf = 1000 pf, t a = 25c, 52.3 termination resistor at inhi, unless otherwise noted. table 1. parameter conditions min typ max unit signal input interface inhi (pin 1) specified frequency range 0.001 10 ghz dc common-mode voltage v pos ? 0.6 v measurement mode vout (pin 5) shorted to vset (pin 4), sinusoidal input signal f = 900 mhz r tadj = 18 k input impedance 1500||0.33 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 40 db maximum input level 1 db error ?3 dbm minimum input level 1 db error ?43 dbm slope 1 ?25 ?22 ?19.5 mv/db intercept 1 12 15 21 dbm output voltage: high power in p in = ?10 dbm 0.57 v output voltage: low power in p in = ?40 dbm 1.25 v f = 1.9 ghz r tadj = 8 k input impedance 950||0.38 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 40 db maximum input level 1 db error ?4 dbm minimum input level 1 db error ?44 dbm slope 1 ?25 ?22 ?19.5 mv/db intercept 1 10 13 20 dbm output voltage: high power in p in = ?10 dbm 0.53 v output voltage: low power in p in = ?35 dbm 1.19 v f = 2.2 ghz r tadj = 8 k input impedance 810||0.39 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 40 db maximum input level 1 db error ?5 dbm minimum input level 1 db error ?45 dbm slope 1 ?22 mv/db intercept 1 13 dbm output voltage: high power in p in = ?10 dbm 0.5 v output voltage: low power in p in = ?35 dbm 1.18 v f = 3.6 ghz r tadj = 8 k input impedance 300||0.33 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 36 db maximum input level 1 db error ?6 dbm minimum input level 1 db error ?46 dbm slope 1 ?22 mv/db intercept 1 10 dbm output voltage: high power in p in = ?10 dbm 0.46 v output voltage: low power in p in = ?40 dbm 1.14 v
ad8319 rev. b | page 4 of 20 parameter conditions min typ max unit f = 5.8 ghz r tadj = 500 input impedance 110||0.05 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 40 db maximum input level 1 db error ?3 dbm minimum input level 1 db error ?43 dbm slope 1 ?22 mv/db intercept 1 15 dbm output voltage: high power in p in = ?10 dbm 0.57 v output voltage: low power in p in = ?40 dbm 1.25 v f = 8.0 ghz r tadj = open input impedance 28||0.79 ||pf 1 db dynamic range t a = 25c 40 db ?40c < t a < +85c 31 db maximum input level 1 db error ?1 dbm minimum input level 1 db error ?41 dbm slope 2 ?22 mv/db intercept 2 20 dbm output voltage: high power in p in = ?10 dbm 0.67 v output voltage: low power in p in = ?40 dbm 1.34 v output interface vout (pin 5) voltage swing v set = 0 v; rfin = open v pos ? 0.1 v v set = 1.5 v; rfin = open 10 mv output current drive v set = 0 v; rfin = open 10 ma small signal bandwidth rfin = ?10 dbm; from clpf to vout 140 mhz output noise rfin = 2.2 ghz, ?10 dbm, f noise = 100 khz, c lpf = open 90 nv/hz fall time input level = no signal to ?10 dbm, 90% to 10%; c lpf = 8 pf 18 ns input level = no signal to ?10 dbm, 90% to 10%; c lpf = open; r out = 150 6 ns rise time input level = ?10 dbm to no signal, 10% to 90%; c lpf = 8 pf 20 ns input level = ?10 dbm to no signal, 10% to 90%; c lpf = open; r out = 150 10 ns video bandwidth (or envelope bandwidth) 50 mhz vset interface vset (pin 4) nominal input range rfin = 0 dbm; measurement mode 0.35 v rfin = ?40 dbm; measurement mode 1.23 v logarithmic scale factor ?45 db/v input resistance rfin = ?20 dbm; controller mode; v set = 1 v 40 k tadj interface tadj (pin 6) input resistance tadj = 0.9 v, sourcing 50 a 40 k disable threshold voltage tadj = open v pos ? 0.4 v power interface vpos (pin 7) supply voltage 3.0 5.5 v quiescent current 18 22 30 ma vs. temperature ?40c t a +85c 60 a/c disable current tadj = vpos 200 a 1 slope and intercept are determined by calculating the best fit line between the power levels of ?40 dbm and ?10 dbm at the spe cified input frequency. 2 slope and intercept are determined by calculating the best fit line between the power levels of ?34 dbm and ?16 dbm at 8.0 ghz .
ad8319 rev. b | page 5 of 20 absolute maximum ratings table 2. parameter rating supply voltage: v pos 5.7 v v set voltage 0 to v pos input power (single-ended, re: 50 ) 12 dbm internal power dissipation 0.73 w ja 55c/w maximum junction temperature 125c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad8319 rev. b | page 6 of 20 pin configuration and fu nction descriptions 1 inhi 2 comm 3 clpf 4 vset 8inlo 7 vpos 6 tadj 5vout top view (not to scale) ad8319 05705-002 figure 2. pin configuration table 3. pin function descriptions pin o. nemonic description 1 inhi rf input. nominal input range of ?50 db m to 0 dbm, re: 50 ; ac-coupled rf input. 2 comm device common. connect this pin to a low impedance ground plane. 3 clpf loop filter capacitor. in measurement mode, this capacito r sets the pulse response time and video bandwidth. in controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. 4 vset setpoint control input for controller mode or feedback input for measurement mode. 5 vout measurement and controller output. in measurement mode, vout provides a decreasing linear-in-db representation of the rf input signal amplitude. in controller mode, vout is us ed to control the gain of a vga or vva with a positive gain sense (increasing voltage increases gain). 6 tadj temperature compensation adjustment. frequency depend ent temperature compensation is set by connecting a ground referenced resistor to this pin. 7 vpos positive supply voltage, 3.0 v to 5.5 v. 8 inlo rf common for inhi. ac-coupled rf common. paddle the paddle is internally connected to comm; solder to a low impedance ground plane.
ad8319 rev. b | page 7 of 20 typical performance characteristics v pos = 3 v; t = 25c, ?40c, +85c; c lpf = 1000 pf; unless otherwise noted. black: 25c; blue: ?40c; red: +85c. error is calculated by using the best fit line between p in = ?40 dbm and p in = ?10 dbm at the specified input frequency, unless otherwise noted. 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-003 figure 3. v out and log conformance error vs. input amplitude at 900 mhz, r tadj = 18 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-004 figure 4. v out and log conformance error vs. input amplitude at 1.9 ghz, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-005 figure 5. v out and log conformance error vs. input amplitude at 2.2 ghz, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-006 figure 6. v out and log conformance error vs. input amplitude at 3.6 ghz, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-007 figure 7. v out and log conformance error vs. input amplitude at 5.8 ghz, r tadj = 500 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-008 figure 8. v out and log conformance error vs. input amplitude at 8.0 ghz, r tadj = open, error calculated from p in = ?34 dbm to p in = ?16 dbm
ad8319 rev. b | page 8 of 20 05705-009 v out (v) 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 0.75 error (db) ?2.0 ?1.5 ?1.0 0 0.5 1.0 1.5 2.0 ?0.5 p in (dbm) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 figure 9. v out and log conformance error vs. input amplitude at 900 mhz, multiple devices, r tadj = 18 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-010 figure 10. v out and log conformance error vs. input amplitude at 1.9 ghz, multiple devices, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-011 figure 11. v out and log conformance error vs. input amplitude at 2.2 ghz, multiple devices, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-012 figure 12. v out and log conformance error vs. input amplitude at 3.6 ghz, multiple devices, r tadj = 8 k 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-013 figure 13. v out and log conformance error vs. input amplitude at 5.8 ghz, multiple devices, r tadj = 500 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 error (db) ?0.5 ?1.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 p in (dbm) 05705-014 figure 14. v out and log conformance error vs. input amplitude at 8.0 ghz, multiple devices, r tadj = open, error calculated from p in = ?34 dbm to p in = ?16 dbm
ad8319 rev. b | page 9 of 20 0 j2 j 1 ?j1 ?j2 j0.5 ?j0.5 j0.2 ?j0.2 0.2 0.5 1 2 8000mhz 10000mhz 5800mhz 3600mhz 2200mhz 1900mhz 900mhz 100mhz s tart frequency = 0.05ghz s top frequency = 10ghz 05705-015 figure 15. input impedance vs. frequency; no termination resistor on inhi (impedance de-embedded to input pins), z 0 = 50 500mv 05705-016 m2.00s a ch1 420v t 29.60% ch1 1 ? : 1.53v @ : 1.53v figure 16. power on/off response time; v p = 3.0 v; input ac-coupling capacitors = 10 pf; c lpf = open 200mv 05705-017 m20.0ns a ch1 1.04v t 72.40% ch1 1 ch1 rise 9.949ns ch1 fal l 6.032ns figure 17. v out pulse response time; pulsed rf input 0.1 ghz, ?10 dbm; c lpf = open; r load = 150 05705-018 1k 10k 100k 1m 10 100 1k 10k 10m noise spectral density (nv/ hz) 0dbm rf off frequency (hz) ?60dbm ?10dbm ?40dbm ?20dbm figure 18. noise spectral densit y of output vs. frequency; c lpf = open 05705-019 1k 10k 100k 1m 10 100 1k 10k 10m noise spectral density (nv/ hz) frequency (hz) figure 19. noise spectral density of output buffer vs. frequency (from clpf to vout); c lpf = 0.1 f 0 0.25 0.50 1.00 1.25 1.50 1.75 2.00 v out (v) 0.75 error (db) ?2.0 ?1.5 0 0.5 1.0 1.5 2.0 ?0.5 ?1.0 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 p in (dbm) ?60 3.3v 3.0v 3.6v 05705-020 figure 20. v out stability and error vs. supply voltage at 1.9 ghz when v pos varies by 10%
ad8319 rev. b | page 10 of 20 theory of operation the ad8319 is a five-stage demodulating logarithmic amplifier, specifically designed for use in rf measurement and power control applications at frequencies up to 10 ghz. a block diagram is shown in figure 21 . sharing much of its design with the ad8318 logarithmic detector/controller, the ad8319 maintains tight intercept variability vs. temperature over a 40 db range. additional enhancements over the ad8318 , such as reduced rf burst response time of 6 ns to 10 ns, 22 ma supply current, and board space requirements of only 2 mm 3 mm add to the low cost and high performance benefits found in the ad8319. gain bias slope det det det det inhi inlo iv v ou t vset clpf tadj v pso comm 05705-021 iv figure 21. block diagram a fully differential design, using a proprietary, high speed sige process, extends high frequency performance. input inhi receives the signal with a low frequency impedance of nominally 500 in parallel with 0.7 pf. the maximum input with 1 db log conformance error is typically 0 dbm (re: 50 ). the noise spectral density referred to the input is 1.15 nv/hz, which is equivalent to a voltage of 118 v rms in a 10.5 ghz bandwidth or a noise power of ?66 dbm (re: 50 ). this noise spectral density sets the lower limit of the dynamic range. however, the low end accuracy of the ad8319 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. the common pin, comm, provides a quality low impedance connection to the pcb ground. the package paddle, which is internally connected to the comm pin, should also be grounded to the pcb to reduce thermal impedance from the die to the pcb. the logarithmic function is approximated in a piecewise fashion by five cascaded gain stages. (for a detailed explanation of the logarithm approximation, refer to the ad8307 data sheet.) the cells have a nominal voltage gain of 9 db each and a 3 db bandwidth of 10.5 ghz. using precision biasing, the gain is stabilized over temperature and supply variations. the overall dc gain is high due to the cascaded nature of the gain stages. an offset compensation loop is included to correct for offsets within the cascaded cells. at the output of each of the gain stages, a square-law detector cell is used to rectify the signal. the rf signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. along with the five gain stages and detector cells, an additional detector is included at the input of the ad8319, providing a 40 db dynamic range in total. after the detector currents are summed and filtered, the following function is formed at the summing node: i d log 10 ( v in / v intercept ) (1) where: i d is the internally set detector current. v in is the input signal voltage. v intercept is the intercept voltage (that is, when v in = v intercept , the output voltage would be 0 v, if it were capable of going to 0 v).
ad8319 rev. b | page 11 of 20 using the ad8319 basic connections the ad8319 is specified for operation up to 10 ghz, as a result, low impedance supply pins with adequate isolation between functions are essential. a power supply voltage of between 3.0 v and 5.5 v should be applied to vpos. power supply decoupling capacitors of 100 pf and 0.1 f should be connected close to this power supply pin. 05705-022 ad8319 1 2 3 4 8 7 6 5 signal input notes 1. see the temperature compensation of the output voltage section. 2. see the output filtering section. r1 52.3 ? r2 0 ? r4 0 ? c2 47nf c1 47nf c5 0.1f c4 100pf v s (3.0v to 5.5v) inhi inlo vpos tadj vout comm clpf vset see note 1 v out see note 2 figure 22. basic connections the paddle of the lfcsp is internally connected to comm. for optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane. input signal coupling the rf input (inhi) is single-ended and must be ac-coupled. inlo (input common) should be ac-coupled to ground. suggested coupling capacitors are 47 nf ceramic 0402-style capacitors for input frequencies of 1 mhz to 10 ghz. the coupling capacitors should be mounted close to the inhi and inlo pins. the coupling capacitor values can be increased to lower the high-pass cutoff frequency of the input stage. the high-pass corner is set by the input coupling capacitors and the internal 10 pf high-pass capacitor. the dc voltage on inhi and inlo is approximately one diode voltage drop below v pos . 05705-023 v pos 2k ? a = 9db 18.7k ? 18.7k ? current gm stage inlo inhi offset comp 5pf 5pf first gain stage figure 23. input interface although the input can be reactively matched, in general, this is not necessary. an external 52.3 shunt resistor (connected on the signal side of the input coupling capacitors, as shown in figure 22 ) combines with the relatively high input impedance to give an adequate broadband 50 match. the coupling time constant, 50 c c /2, forms a high-pass corner with a 3 db attenuation at f hp = 1/(2 50 c c ), where c1 = c2 = c c . using the typical value of 47 nf, this high-pass corner is ~68 khz. in high frequency applications, f hp should be as large as possible to minimize the coupling of unwanted low frequency signals. in low frequency applications, a simple rc network forming a low-pass filter should be added at the input for similar reasons. this should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. output interface the vout pin is driven by a pnp output stage. an internal 10 resistor is placed in series with the output and the vout pin. the rise time of the output is limited mainly by the slew on clpf. the fall time is an rc-limited slew given by the load capacitance and the pull-down resistance at vout. there is an internal pull-down resistor of 1.6 k. a resistive load at vout is placed in parallel with the internal pull-down resistor to provide additional discharge current. 05705-024 + 0.8v 1200 ? 400 ? ? 10? v ou t v pos clpf c omm figure 24. output interface to reduce the fall time, vout should be loaded with a resistive load of <1.6 k. for example, with an external load of 150 , the ad8319 fall time is <7 ns. setpoint interface the v set input drives the high impedance input (40 k) of an internal op amp. the v set voltage appears across the internal 1.5 k resistor to generate i set . when a portion of v out is applied to vset, the feedback loop forces ?i d log 10 ( v in / v intercept ) = i set (2) if v set = v out /2x, i set = v out /(2x 1.5 k). the result is v out = ( ?i d 1.5 k 2x) log 10 ( v in / v intercept ) 05705-025 1.5k ? i set comm v set v set comm 20k ? 20k ? figure 25. vset interface
ad8319 rev. b | page 12 of 20 the slope is given by ?i d 2x 1.5 k = ?22 mv/db x. for example, if a resistor divider to ground is used to generate a v set voltage of v out /2, x = 2. the slope is set to ?880 mv/decade or ?44 mv/db. temperature compensa tion of output voltage the primary component of the variation in v out vs. temperature, as the input signal amplitude is held constant is the drift of the intercept. this drift is also a weak function of the input signal frequency; therefore, provision is made for optimization of internal temperature compensation at a given frequency by providing the tadj pin. comm comm i comp v internal tadj r tadj 05705-026 1.5k ? ad8319 figure 26. tadj interface r tadj is connected between this pin and ground. the value of this resistor partially determines the magnitude of an analog correction coefficient, which is used to reduce intercept drift. the relationship between output temperature drift and frequency is not linear and cannot be easily modeled. as a result, experimentation is required to choose the correct tadj resistor. table 4 shows the recommended values for some commonly used frequencies. table 4. recommended r tadj resistor values frequency recommended r tadj 50 mhz 18 k 100 mhz 18 k 900 mhz 18 k 1.8 ghz 8 k 1.9 ghz 8 k 2.2 ghz 8 k 3.6 ghz 8 k 5.3 ghz 500 5.8 ghz 500 8 ghz open measurement mode when the v out voltage or a portion of the v out voltage is fed back to the vset pin, the device operates in measurement mode. as seen in figure 27 , the ad8319 has an offset voltage, a negative slope, and a v out measurement intercept at the high end of its input signal range. 0 0.25 0.50 0.75 1.00 1.25 1.50 2.00 v out (v) error (db) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 p in (dbm) 05705-027 range for calculation of slope and intercept v out 25c error 25c intercept 1.75 figure 27. typical output voltage vs. input signal the output voltage vs. input signal voltage of the ad8319 is linear-in-db over a multidecade range. the equation for this function is v out = x v slope/dec log 10 ( v in / v intercept ) = x v slope/db 20 log 10 ( v in / v intercept ) (3) where: x is the feedback factor in v set = v out /x. v slope/dec is nominally ?440 mv/decade or ?22 mv/db. v intercept is the x-axis intercept of the linear-in-db portion of the v out vs. p in curve (see figure 27 ). v intercept is 15 dbm (2 dbv) for a sinusoidal input signal. an offset voltage, v offset , of 0.35 v is internally added to the detector signal, so that the minimum value for v out is x v offset , so for x = 1, minimum v out is 0.35 v. the slope is very stable vs. process and temperature variation. when base-10 logarithms are used, v slope/dec represents the volts/decade. a decade corresponds to 20 db; v slope/dec /20 = v slope/db represents the slope in volts/db. b as noted in the equation 1 and equation 2, the v out voltage has a negative slope. this is also the correct slope polarity to control the gain of many power amplifiers in a negative feedback configu- ration. because both the slope and intercept vary slightly with frequency, it is recommended to refer to the specifications section for application-specific values for the slope and intercept. although demodulating log amps respond to input signal voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. in this case, the characteristic impedance of the system, z 0 , must be known to convert voltages to their corresponding power levels. equation 4 to equation 6 are used to perform this conversion. p (dbm) = 10 log 10 ( v rms 2 /( z 0 1 mw)) (4) p (dbv) = 20 log 10 ( v rms /1 v rms ) (5) p (dbm) = p (dbv) ? 10 log 10 ( z 0 1 mw/1 v rms 2 ) (6)
ad8319 rev. b | page 13 of 20 for example, p intercept for a sinusoidal input signal expressed in terms of dbm (decibels referred to 1 mw), in a 50 system is p intercept (dbm) = p intercept (dbv) ? 10 log 10 ( z 0 1 mw/1 v rms 2 ) = 2 dbv ? 10 log 10 (5010 -3 ) = 15 dbm (7) for a square wave input signal in a 200 system p intercept = ?1 dbv ? 10 log 10 [(200 1 mw/1v rms 2 )] = 6 dbm further information on the intercept variation dependence upon waveform can be found in the ad8313 and ad8307 data sheets. setting the output slope in measurement mode to operate in measurement mode, vout must be connected to vset. connecting vout directly to vset yields the nominal logarithmic slope of ?22 mv/db. the output swing corresponding to the specified input range is then 0.35 v to 1.5 v. the slope and output swing can be increased by placing a resistor divider between vout and vset (that is, one resistor from vout to vset and one resistor from vset to ground). the input imped- ance of vset is 40 k. slope setting resistors should be kept below 20 k to prevent this input impedance from affecting the resulting slope. if two equal resistors are used (for example, 10 k/10 k), the slope doubles to ?44 mv/db. 05705-028 vout ad8319 ?44mv/db vset 10k ? 10k ? controller mode the ad8319 provides a controller mode feature at the vout pin. using v set for the setpoint voltage, it is possible for the ad8319 to control subsystems, such as power amplifiers (pas), variable gain amplifiers (vgas), or variable voltage attenuators (vvas) that have output power that increases monotonically with respect to their gain control signal. to operate in controller mode, the link between vset and vout is broken. a setpoint voltage is applied to the vset input; vout is connected to the gain control terminal of the vga and the rf input of the detector is connected to the output of the vga (usually using a directional coupler and some additional attenuation). based on the defined relationship between v out and the rf input signal when the device is in measurement mode, the ad8319 adjusts the voltage on vout (vout is now an error amplifier output) until the level at the rf input corresponds to the applied v set . when the ad8319 operates in controller mode, there is no defined relationship between the v set and v out voltages; v out settles to a value that results in the correct input signal level appearing at inhi/inlo. for this output power control loop to be stable, a ground- referenced capacitor must be connected to the clpf pin. this capacitor, c flt , integrates the error signal (in the form of a current) to set the loop bandwidth and ensure loop stability. further details on control loop dynamics can be found in the ad8315 data sheet. 05705-029 rfin vga/vva gain control voltage directional coupler attenuator inhi vset inlo clpf vout ad8319 52.3 ? 47nf c flt 47nf dac figure 29. controller mode decreasing v set , which corresponds to demanding a higher signal from the vga, increases v out . the gain control voltage of the vga must have a positive sense. a positive control voltage to the vga increases the gain of the device.
ad8319 rev. b | page 14 of 20 inlo inhi gain oplo ophi directional coupler attenuator vpos comm adl5330 +5v +5v +5 v comm vout vpos vset inhi inlo clpf ad8319 log amp dac rf output signal 4.12k ? 10k ? setpoint voltage 1nf 47nf 47nf 120nh 120nh 100pf 100pf 100pf 100pf tadj 18k ? 52.3 ? rf input signal 05705-030 figure 30. ad8319 operating in controller mode to provide automatic gain control functionality in combination with the adl5330 the basic connections for operating the ad8319 in an automatic gain control (agc) loop with the adl5330 are shown in figure 30 . the adl5330 is a 10 mhz to 3 ghz vga. it offers a large gain control range of 60 db with 0.5 db gain stability. this configuration is similar to figure 29 . the gain of the adl5330 is controlled by the output pin of the ad8319. this voltage, v out , has a range of 0 v to near v pos . to avoid overdrive recovery issues, the ad8319 output voltage can be scaled down using a resistive divider to interface with the 0 v to 1.4 v gain control range of the adl5330 . a coupler/attenuation of 21 db is used to match the desired maximum output power from the vga to the top end of the linear operating range of the ad8319 (approximately ?5 dbm at 900 mhz). figure 31 shows the transfer function of the output power vs. the v set voltage over temperature for a 900 mhz sine wave with an input power of ?1.5 dbm. note that the power control of the ad8319 has a negative sense. decreasing v set , which corresponds to demanding a higher signal from the adl5330 , increases gain. the agc loop is capable of controlling signals of ~40 db. this range limitation is due to the dynamic range of the ad8319. using a wider dynamic range detector, such as the ad8317 , ad8318 , or ad8362 , allows for the full 60 db range of the adl5330 to be used. the performance over temperature is most accurate over the highest power range, where it is generally most critical. across the top 40 db range of output power, the linear conformance error is well within 0.5 db over temperature. ?50 ?40 ?30 ?10 0 10 20 30 output power (dbm) ?20 ?4 ?3 0 1 2 3 4 ?1 ?2 error (db) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 setpoint voltage (v) 1.3 1.1 0.3 0.5 0.7 0.9 1.5 1.6 05705-031 figure 31. adl5330 output power vs. ad8319 setpoint voltage, p in = ?1.5 dbm
ad8319 rev. b | page 15 of 20 for the agc loop to remain in equilibrium, the ad8319 must track the envelope of the output signal of the adl5330 and provide the necessary voltage levels to the gain control input of the adl5330 . figure 32 shows an oscilloscope screenshot of the agc loop depicted in figure 30 . a 100 mhz sine wave with 50% am modulation is applied to the adl5330 . the output signal from the vga is a constant envelope sine wave with amplitude corresponding to a setpoint voltage at the ad8319 of 1.3 v. the gain control response of the ad8319 to the changing input envelope is also shown. ch1 200mv a ch2 1.03v 05705-032 m2.00ms t 0.00000 s 1 ch2 200mv am modulated input ad8319 output ch3 100mv ? 2 3 adl5330 output figure 32. oscilloscope screenshot showing an am modulated input signal and the response from the ad8319 figure 33 shows the response of the agc rf output to a pulse on vset. as v set decreases from 1.5 v to 0.4 v, the agc loop responds with an rf burst. in this configuration, the input signal to the adl5330 is a 1 ghz sine wave at a power level of ?15 dbm. a ch1 2.60v t 179.800s ad8319 vset pulse adl5330 output 3 1 m10.s ch1 2.00v ch3 50mv ? 05705-033 t figure 33. oscilloscope screenshot showing the response time of the agc loop response time and the amount of signal integration are controlled by c flt . this functionality is analogous to the feedback capacitor around an integrating amplifier. while it is possible to use large capacitors for c flt , in most applications, values under 1 nf provide sufficient filtering. calibration in controller mode is similar to the method used in measurement mode. a simple two-point calibration can be done by applying two known v set voltages or dac codes and measuring the output power from the vga. slope and intercept can then be calculated by: slope = ( v set1 ? v set2 )/( p out1 ? p out2 ) (8) intercept = p out1 ? v set1 / slope (9) v setx = slope ( p outx ? intercept ) (10) more information on the use of the adl5330 in agc applications can be found in the adl5330 data sheet. output filtering for applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the clpf pin be left unconnected and free of any stray capacitance. the nominal output video bandwidth of 50 mhz can be reduced by connecting a ground-referenced capacitor (c flt ) to the clpf pin, as shown in figure 34 . this is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). +4 vout clpf ad8319 3.5pf 05705-037 i log c flt 1.5k ? figure 34. lowering the po stdemodulation bandwidth c flt is selected by pf3.5 k 1.52 1 uu bandwidth video c flt (11) the video bandwidth should typically be set to a frequency equal to approximately one-tenth the minimum input frequency. this ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. in many log amp applications, it may be necessary to lower the corner frequency of the postdemodulation filtering to achieve low output ripple while maintaining a rapid response time to changes in signal level. an example of a four-pole active filter is shown in the ad8307 data sheet.
ad8319 rev. b | page 16 of 20 operation beyond 8 ghz the ad8319 is specified for operation up to 8 ghz, but it provides useful measurement accuracy over a reduced dynamic range of up to 10 ghz. figure 35 shows the performance of the ad8319 over temperature at 10 ghz when the device is configured as shown in figure 22 . dynamic range is reduced at this frequency, but the ad8319 does provide 30 db of measurement range within 3 db of linearity error. 05705-038 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 p in (dbm) v out (v) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 error (db) figure 35. v out and log conformance error vs. input amplitude at 10 ghz, multiple devices, r tadj = open, c lpf = 1000 pf implementing an impedance match for frequencies beyond 8 ghz can improve the sensitivity of the ad8319 and measurement range. operation beyond 10 ghz is possible, but part-to-part variation, most notably in the intercept, becomes significant.
ad8319 rev. b | page 17 of 20 evaluation board ad8319 1 2 3 4 8 7 6 5 r1 52.3 ? r7 open r2 0 ? c1 c2 c4 c5 47nf 47nf 0.1f 100pf v pos inhi inlo vpos tadj vout comm clpf vset 05705-034 t a dj r5 200 ? r4 open vout_alt r3 open cl open rl open r6 1k ? gnd rfin v set v ou t c3 8.2pf figure 36. evaluation board schematic (rev. a) table 5. evaluation board (rev. a) configuration options component function default conditions vpos, gnd supply and ground connections. not applicable r1, c1, c2 input interface. the 52.3 resistor in position r1 combines wi th the internal input impedance of the ad8319 to give a broadband input impedance of approximatel y 50 . capacitor c1 and capacitor c2 are dc blocking capacitors. a reactive impedance match can be implemented by replacing r1 with an inductor and c1 and c2 with ap propriately valued capacitors. r1 = 52.3 (size 0402) c1 = 47 nf (size 0402) c2 = 47 nf (size 0402) r5, r7 temperature compensation interface. the internal temperature compensation network is optimized for input signals up to 3.6 ghz when r7 is 10 k. this circuit can be adjusted to optimize performance for other input frequencies by changing the value of the resistor in position r7. see table 4 for specific r tadj resistor values. r5 = 200 (size 0402) r7 = open (size 0402) r2, r3, r4, r6, rl, cl output interfacemeasurement mode. in measurement mode, a portion of the output volt age is fed back to the vset pin via r2. the magnitude of the slope of the vout output voltag e response can be increased by reducing the portion of v out that is fed back to vset. r6 can be used as a back-terminating resistor or as part of a single-pole, low-pass filter. r2 = 0 (size 0402) r3 = open (size 0402) r4 = open (size 0402) r6 = 1 k (size 0402) rl = cl = open (size 0402) r2, r3 output interfacecontroller mode. in this mode, r2 must be open. in controll er mode, the ad8319 can control the gain of an external component. a setpoint voltage is applied to the vset pin, the value of which corresponds to the desired rf input signal level applied to the ad8319 rf input. a sample of the rf output signal from this variable-gain component is selected, typically via a directional coupler, and applied to ad8319 rf input. the voltage at the vo ut pin is applied to the gain control of the variable gain element. a control voltage is applied to the vset pin. the magnitude of the control voltage can optionally be attenuated via the voltage divider comprising r2 and r3, or a capacitor can be installed in position r3 to form a low-pass filter along with r2. r2 = open (size 0402) r3 = open (size 0402) c4, c5 power supply decoupling. the nominal supply decoupling consists of a 100 pf filter capacitor placed physically close to the ad8319 and a 0.1 f capacitor placed physic ally close to the power supply input pin. c4 = 0.1 f (size 0603) c5 = 100 pf (size 0402) c3 filter capacitor. the low-pass corner frequency of the circuit that drives the vout pin can be lowered by placing a capacitor between clpf and ground. increasing this capacitor increases the overall rise/fall time of the ad8319 for pulsed input signals. see the output filtering section for more details. c3 = 8.2 pf (size 0402)
ad8319 rev. b | page 18 of 20 0 5705-035 figure 37. component side layout 05705-036 figure 38. component side silkscreen
ad8319 rev. b | page 19 of 20 outline dimensions 031207-a 0.30 0.23 0.18 seating plane 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 1.89 1.74 1.59 0.50 bsc 0.60 0.45 0.30 0.55 0.40 0.30 0.15 0.10 0.05 0.25 0.20 0.15 bottom view 4 1 5 8 3.25 3.00 2.75 1.95 1.75 1.55 2.95 2.75 2.55 pin 1 indicator 2.25 2.00 1.75 top view 0.05 max 0.02 nom 12 max exposedpad figure 39. 8-lead lead frame chip scale package [lfcsp_vd] 2 mm 3 mm body, very thin, dual lead (cp-8-1) dimensions shown in millimeters ordering guide model temperature range package description package option branding ad8319acpz-r7 1 C40c to +85c 8-lead lfcsp_vd cp-8-1 q2 AD8319ACPZ-R2 1 C40c to +85c 8-lead lfcsp_vd cp-8-1 q2 ad8319acpz-wp 1 C40c to +85c 8-lead lfcsp_vd, waffle pack cp-8-1 q2 ad8319-evalz 1 evaluation board 1 z = rohs compliant part.
ad8319 rev. b | page 20 of 20 notes ?2005C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05705-0-4/08(b)

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